Semiconductor device structures including energy barriers, and related methods

ABSTRACT

A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.13/612,376, filed Sep. 12, 2012, pending, which application is adivisional of U.S. patent application Ser. No. 12/329,185, filed Dec. 5,2008, now U.S. Pat. No. 8,330,170, issued Dec. 11, 2012, the disclosureof each of which is hereby incorporated herein in its entirety by thisreference.

TECHNICAL FIELD

Embodiments of the present invention relate generally to semiconductordevice structures that are configured to reduce or eliminate the leakageof stored charge, or “junction leakage,” from transistor channels. Morespecifically, embodiments of the present invention relate tosemiconductor devices in which energy barriers are disposed adjacent totransistor channels and, even more specifically, to semiconductordevices with energy barriers that comprise silicon carbide.

BACKGROUND

In nMOS (n-type metal-oxide-semiconductor) transistors, the transistorchannels comprise n-type semiconductor material, in which electronscomprise the majority of charge carriers, and holes are, the carriersthat store charge. The n-type channels of such devices are sometimesformed in a bulk substrate that comprises a p-type semiconductormaterial, in which the majority of charge carriers comprise holes. Thememory data retention times of some nMOS transistors (e.g., floatingbody effect- (FBE-) based 1TOC DRAM cells) depend at least partiallyupon the length of time that the holes, which have a tendency to“travel” into the p-type semiconductor material of the bulk substrate,may be retained within the n-type channels.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a schematic representation of an embodiment of a semiconductordevice structure that includes an energy barrier beneath at least onetransistor;

FIG. 2 illustrates an embodiment of a transistor according to thepresent invention with embedded active device regions;

FIG. 3 depicts an embodiment of a fin field effect transistor (fin FET)according to the present invention;

FIGS. 4 and 4A show other embodiments of “pseudo” silicon-on-insulatorfin FETs of the present invention;

FIG. 5 is an energy band diagram of a transistor of the presentinvention in a “0” condition; and

FIG. 6 is an energy band diagram of a transistor of the presentinvention in a “1” condition.

DETAILED DESCRIPTION

The present invention, in various embodiments, includes semiconductordevice structures with transistors that include channels that areconfigured for minimal junction leakage. An energy barrier with physicalproperties (e.g., a band gap, a low intrinsic concentration of chargecarriers, etc.) is located against a transistor channel to preventleakage of storage charge carriers from the transistor channel into thebulk substrate upon which the semiconductor device has been fabricated.

An embodiment of a semiconductor device structure 10 of the presentinvention is depicted by FIG. 1. Semiconductor device structure 10includes one or more transistors 12 fabricated upon and/or carried by afabrication substrate 14. Fabrication substrate 14 includes a basesubstrate 16, an energy barrier 18 on at least some portions of acarrier surface 17 of base substrate 16, and a semiconductor film 20 onat least portions of energy barrier 18. Elements of a transistor 12,including source and drain regions 22, 24 and a channel 26 betweensource and drain regions 22, 24, are formed from semiconductor film 20,with a gate 28 of transistor 12 being formed on an opposite side ofsemiconductor film 20 from energy barrier 18.

Embodiments of substrates that may be used as base substrate 16 include,but are not limited to, full or partial bulk semiconductor substrates(e.g., full or partial silicon wafers, etc.) or full or partialsilicon-on-insulator (SOD type substrates (e.g., silicon-on-ceramic(SOC), silicon-on-glass (SOG), silicon-on-sapphire (SOS), etc.). Inother embodiments, base substrate 16 may comprise a dielectric material,such as quartz, ceramic, sapphire, etc., without an overlying layer ofsemiconductor material.

Energy barrier 18, or an interface 19 between energy barrier 18 and theadjacent semiconductor film 20, inhibits the loss of charge carriers(e.g., holes), or, more simply, “carriers,” from a transistor 12 on oneside of energy barrier 18. In embodiments where energy barrier 18 isdisposed against a carrier surface 17 of base substrate 16 thatcomprises a semiconductor material, either in bulk or as a layer formedupon a support structure, of base substrate 16, energy barrier 18 mayprevent carriers from passing from transistor 12 into the semiconductormaterial of base substrate 16.

The properties of energy barrier 18, or of the interface 19 betweenenergy barrier 18 and the overlying semiconductor film 20, may beattributed to physical properties of the material or materials fromwhich energy barrier 18 is formed, including differences between thoseproperties and corresponding properties of semiconductor film 20, thethickness of energy barrier 18, or a combination of the foregoing. Insome embodiments, energy barrier 18 comprises a material with a bandgapenergy (e.g., about 1.5 eV or greater, about 3 eV or greater, etc.) thatis greater than the bandgap energy of silicon (i.e., 1.12 eV). Such amaterial may have an intrinsic concentration of carriers (e.g., holes)that is lower than the intrinsic concentration of the same type ofcarriers in the semiconductor material of base substrate 16.

An energy barrier 18 may have any thickness suitable for preventing thepassage of carriers from a transistor on one side to the semiconductormaterial of the base substrate 16 on the opposite side. In someembodiments where energy barrier 18 comprises a silicon carbide, energybarrier 18 may have a thickness of about 50 nm (about 500 Å) to about150 nm (about 1,500 Å). Of course, embodiments with energy barriers 18that have other thicknesses are also within the scope of the presentinvention.

Silicon carbide (SiC) is a specific embodiment of a material from whichenergy barrier 18 may be formed. Silicon carbide has an intrinsicconcentration of electron carriers that may be about 1/10¹⁶ (or 10⁻¹⁶)of the intrinsic concentration of electron carriers in singlecrystalline silicon. More specific embodiments of silicon carbideinclude the hexagonal (H) polytypes of SiC that are known as “4H-SiC”and “6H-SiC” and the cubic (C) polytype that is known as “3C-SiC.” Thefollowing table compares various properties of 4H-SiC and 6H-SiC to thecorresponding properties of silicon:

TABLE 4H-SiC 6H-SiC Silicon Bandgap Energy (eV) 3.26 3.03 1.112 MaximumDrift Velocity 2.0 × 10⁷ 2.0 × 10⁷ 1.0 × 10⁷ (cm/sec @ E = 2 × 10⁵ V/cm)Thermal Conductivity 3.0 to 3.8 3.0 to 3.8 1.5  (W/cm K @ 300 K)Breakdown Electric Field (V/cm) 2.2 × 10⁶ 2.4 × 10⁶ 2.5 × 10⁵

In embodiments where energy barrier 18 comprises a silicon carbide(SiC), the silicon carbide may be epitaxially grown or otherwisedisposed upon carrier surface 17 by known processes. Embodiments of suchprocesses are described by Miura, H., et al., “Epitaxial Growth of SiCon Silicon on Insulator Substrates with Ultrathin Top Si Layer byHot-Mesh Chemical Vapor Deposition,” Japan J. Appl. Phys 47(1): 569(2008); Steszewski, J., et al., “Comparison of 4H-SiC and 6H-SiC MOSFETI-V characteristics simulated with Silvaco Atlas and Crosslight Apsys,”J. Telecomm. & I.T., March 2007, page 93; Eickhoff, M., “Selectivegrowth of high-quality 3C-SiC using a SiO₂ sacrificial-layer technique,”Thin Solid Films 345(2): 197-99 (1999); Ernst, T., et al., “A new Si:Cepitaxial channel nMOSFET architecture with improved drivability andshort-channel characteristics,” VLSI Symp. 2003:51-52 (2003); and Ernst,T., et al., “Fabrication of a Novel strained SiGe:C-channel planar 55 nmnMOSFET for High-Performance CMOS,” VLSI Symp. 2002:92-93 (2002), thedisclosures of each of Which are hereby incorporated herein, in theirentireties, by this reference. The intrinsic concentration of carriersin the silicon carbide correlates to the temperature at which thesilicon carbide is deposited. In some embodiments, the intrinsicconcentration of carriers in silicon carbide may be low (e.g., about1/10¹⁶ (or 10⁻¹⁶) the intrinsic concentration of carriers insingle-crystalline silicon).

In other embodiments, energy barrier 18 may comprise a so-called“carbonated silicon,” or Si:C, in which as much as about 1.4% of themolecules in the crystalline structure comprise carbon. Methods forforming a carbonated silicon energy barrier 18 are disclosed by Ernst,T., et al., “A new Si:C epitaxial channel nMOSFET architecture withimproved drivability and short-channel characteristics,” 2003 Symposiumon VLSI Technology Digest of Technical Papers, pages 51-52, the entiredisclosure of which is, by this reference, hereby incorporated herein.

In some embodiments, a semiconductor film 20 may be fabricated overenergy barrier 18. Semiconductor film 20 may be fabricated by knownprocesses, such as by the epitaxial growth of silicon upon energybarrier 18. Semiconductor film 20 may, in some embodiments, have athickness of about 50 nm (about 500 Å) to about 150 nm (about 1,500 Å).

With semiconductor film 20 in place upon energy barrier 18, processesthat are known in the art may be used to fabricate transistors 12 fromand upon semiconductor film 20. Such processes include, withoutlimitation, the fabrication of isolation structures, transistorchannels, transistor gate dielectrics, transistor gates, spacers andcaps (if any) for the transistor gates, and source and drain regions.The channels 26 of the resulting transistors 12 may include p-typematerial, in which the carriers are holes, and the source and drain 22,24 may include n-type material. Various embodiments Of the resultingstructures are depicted in FIGS. 2 through 4.

FIG. 2 illustrates an embodiment of a semiconductor device structure 110that includes a transistor 112 with source 122 and drain 124 regions andan intervening channel 126 formed in semiconductor film 20. A gatedielectric 127 is located over channel 126. A transistor gate 128 iscarried by gate dielectric 127 with side wall spacers 130 adjacent toeach side of transistor gate 128 and a cap 132 atop transistor gate 128.An energy barrier 18 is located beneath source 122 and drain 124 andabove a semiconductor material at carrier surface 17 of base substrate16.

In FIG. 3, an embodiment of a so-called “fin field effect transistor”(“fin FET”) 212 is depicted. Each fin 240 of fin FET 212 protrudes fromenergy barrier 18, with a protruding region of energy barrier 18 forminga base 242 of each fin 240 and the top 244 of each fin 240 comprisingsilicon (e.g., silicon defined from semiconductor film 20—FIG. 1). Knownprocesses may be used to define one or more fins 240 from films thatcomprise silicon (to define top 244 of each fin 240 from semiconductorfilm 20) and an energy barrier material (to form base 242 of each fin240 from energy barrier 18). In some embodiments, known mask andanisotropic etch processes may be used to define each fin 240.

A gate dielectric 227 is carried by the surfaces of each fin 240 andextends onto a major surface, depicted as the horizontally extendingsurface, of energy barrier 18. Gate dielectric 227, in turn, carries atransistor gate 228.

In some fin FET embodiments, such as the transistor 212′ shown in FIG.4, an undercut region 250 may be formed in and extend along both sidesof base 242′ of each fin 240′. Each undercut region 250 may be formed byknown processes, such as by the use of an isotropic etchant, alone or inconjunction with known processes (e.g., use of selectively placeddopants in conjunction with the use of appropriate etchants, laserablation techniques, etc.) for limiting the location and size of eachundercut region 250.

Each undercut region 250 may, in some embodiments, be filled with a.dielectric material (e.g., a silicon dioxide, etc.). In the embodimentdepicted by FIG, 4, the dielectric material forms a film 251.Alternatively, in the embodiment depicted by FIG. 4A, dielectricelements 252 may be formed from the dielectric material. The results ofboth of the depicted embodiments are so-called “pseudo SOI” structures,in which a portion of each fin 240′ overlies dielectric material.

In the embodiment shown in FIG. 4A, each dielectric element 252 includesa surface 254 that is coplanar with, or substantially coplanar with, aside wall 241 of its corresponding fin 240′. Dielectric elements 252 maybe formed by introducing (e.g., depositing, etc.) dielectric materialonto an exposed surface of energy barrier 18 to form a dielectric film251, such as that shown in FIG. 4. With the exception of dielectricmaterial located within. undercut regions 250, or beneath other regionsof fins 240′, all or substantially all, of the dielectric material thatoverlies energy barrier 18 may then be removed. In some embodiments,such removal may be effected by anisotropic etch processes. Inembodiments where an etchant is employed that removes the dielectricmaterial with high selectivity over the materials from which each fin240′ has been fabricated, each fin 240′ may be used as a mask during thematerial removal process.

Once transistors 12, 112, 212, 212′ have been fabricated, furtherprocessing, including, without limitation, the formation of interlayerdielectric films, interconnects, conductive lines, and back-end-of-line(BEOL) processing may be effected as known in the art.

With returned reference to FIG. 1, a semiconductor device structure 10of the present invention may, in some embodiments, comprise a dynamicrandom access memory (DRAM) device, such as a DRAM device that includes1TOC memory cells. The use of an energy barrier 18 in conjunction withone or more transistors 12 of such a structure may increase the amountof time that a memory cell associated with that transistor 12 willretain a charge (i.e., retain holes within the transistor channel).

The ability of an energy barrier 18 according to embodiments of thepresent invention to prevent the loss of carriers from a transistor and,thus, to increase the retention in the floating body effect (FBE) ofcarriers within the transistor and the loss of charge stored by way ofthe transistor is depicted by the energy band diagrams of FIGS 5 and 6.

In structures where silicon is adjacent to silicon carbide or carbonatedsilicon, an energy band offset occurs at the interface between thesematerials. FIGS. 5 and 6 both illustrate that the band gap 426, 427 ofthe semiconductor material (e.g., silicon—about 1 eV) of a transistorchannel 26 is less than the band gap 419 of material of an energybarrier 18 adjacent to transistor channel 26.

In FIG. 5, the memory cell is in a “0” condition, with the difference inband gaps represented by a barrier line that corresponds to interface 19(FIG. 1) between semiconductor film 20 and energy barrier 18.

FIG. 6 is an energy band diagram of the same memory cell in a “1”condition. It is apparent from a comparison between FIG. 5 and FIG. 6that the band gaps 426, 427 and 419 of transistor channel 26 and energybarrier 18, respectively, are the same when the memory cell is in bothstates. The ability of interface 19 to retain carriers 450 withintransistor channel 26 is also depicted in FIG. 6, with the heightenedenergy state being represented as a raised peak of portion of the energyband 427 that corresponds to transistor channel 26.

When an energy barrier is incorporated into a transistor, junctionleakage, or the leakage of holes from a transistor channel into the basesubstrate, may be reduced or eliminated.

Although the foregoing description contains many specifics, these shouldnot be construed as limiting the scope of the present invention, butmerely as providing illustrations of some embodiments. Similarly, otherembodiments that are within the scope of the invention may also bedevised. Features from different embodiments may be employed incombination. The scope of the invention is, therefore, indicated andlimited only by the appended claims and their legal equivalents, ratherthan by the foregoing description. All additions, deletions andmodifications to the invention as disclosed herein which fall within themeaning and scope of the claims are to be embraced thereby.

1. A method for increasing charge duration within a channel of atransistor, comprising: forming an energy barrier consisting essentiallyof carbonated silicon on a surface of a base substrate; forming a sourceregion, a drain region, and a silicon channel of a transistor on theenergy barrier; and applying a charge to the channel.
 2. The method ofclaim 1, further comprising accessing the charge stored by the siliconchannel.
 3. The method of claim 1, wherein forming an energy barriercomprises epitaxially forming the energy barrier.
 4. A semiconductordevice, comprising: an energy barrier overlying a base substrate, theenergy barrier consisting essentially of carbonated silicon; and atransistor on the energy barrier and comprising: a source region; adrain region; a channel between the source region and the drain regionand consisting of p-type silicon; and a gate overlying at least portionof the channel.
 5. The semiconductor device of claim 4, wherein thesemiconductor device comprises a dynamic random access memory device. 6.The semiconductor device of claim 4, further comprising a gatedielectric positioned between the channel and the gate.
 7. Thesemiconductor device of claim 4, further comprising: sidewall spacersadjacent opposing sides of at least the gate; and a cap on the gate. 8.The semiconductor device of claim 4, wherein the carbonated siliconcomprises up to about 1.4% carbon atoms.
 9. The semiconductor device ofclaim 4, wherein the energy barrier has a bandgap energy of greater thanabout 1.12 eV.
 10. The semiconductor device of claim 4, wherein theenergy barrier exhibits a thickness within a range of from about 50 nmto about 150 nm.
 11. The semiconductor device of claim 4, wherein thechannel consists of epitaxial, p-type silicon.
 12. The semiconductordevice of claim 4, further comprising silicon dioxide between thechannel and the gate.
 13. A semiconductor device structure, comprising:at least one transistor; and an energy barrier consisting essentially ofepitaxial carbonated silicon underlying an entirety of the at least onetransistor.
 14. The semiconductor device structure of claim 13, whereinthe at least one transistor comprises: a channel consisting essentiallyof epitaxial, p-type silicon on the energy barrier; a source consistingessentially of epitaxial, n-type silicon on the energy barrier andadjacent a first side of the channel; a drain consisting essentially ofepitaxial, n-type silicon on the energy barrier and adjacent a secondside of the channel; and a gate overlying the channel.
 15. Thesemiconductor device structure of claim 14, further comprising: adielectric material on the channel; and spacers adjacent each side ofthe gate.
 16. The semiconductor device structure of claim 13, furthercomprising a semiconductive material directly under the energy barrier.17. The semiconductor device structure of claim 13, wherein thesemiconductive material extends along an entirety of the energy barrier.18. The semiconductor device structure of claim 13, further comprising adielectric material directly under the energy barrier.
 19. Thesemiconductor device structure of claim 13, wherein the energy barrierexhibits a thickness of up to about 150 nanometers.
 20. Thesemiconductor device structure of claim 13, wherein the energy barrierexhibits a bandgap energy of greater than or equal to about 1.5 eV.